Converter apparatus and method with auxiliary transistor for protecting components at startup

ABSTRACT

An apparatus and associated method are provided involving a converter circuit. The converter circuit includes an inductor including a first terminal configured to be coupled to a power source, and a second terminal. Also included is a pair of serially-coupled transistors coupled to the second terminal of the inductor. The pair of serially-coupled transistors have a transistor intermediate node therebetween. Further included is a pair of serially-coupled diodes coupled to the second terminal of the inductor. The pair of serially-coupled diodes have a diode intermediate node therebetween. A first capacitor is coupled in parallel with the serially-coupled transistors and the serially-coupled diodes. Further, the converter circuit includes a sub-circuit having a second capacitor serially-coupled with an auxiliary transistor. The sub-circuit is coupled between the transistor intermediate node and the diode intermediate node.

FIELD

The present disclosure relates to circuits, and more particularly toconverter circuits.

BACKGROUND

Converters are circuits that convert one voltage at an input to anothervoltage at an output. Typically, converters are adapted for receivingvoltage from a power source with a certain polarity configuration.However, if such polarity configuration is improperly applied (e.g.flipped, etc.) at start up, active components (e.g. transistors, diodes,etc.) of the converter may be at risk of undue voltage stress which mayresult in damage or even inoperability.

SUMMARY

Provided is an apparatus including a converter circuit. The convertercircuit comprises an inductor including a first terminal configured tobe coupled to a power source, and a second terminal. Also included is apair of serially-coupled transistors coupled to the second terminal ofthe inductor. The pair of serially-coupled transistors have a transistorintermediate node therebetween. Further included is a pair ofserially-coupled diodes coupled to the second terminal of the inductor.The pair of serially-coupled diodes have a diode intermediate nodetherebetween. A first capacitor is coupled in parallel with theserially-coupled transistors and the serially-coupled diodes. Further,the converter circuit includes a sub-circuit having a second capacitorserially-coupled with an auxiliary transistor. The sub-circuit iscoupled between the transistor intermediate node and the diodeintermediate node.

Also provided is a method for operating a converter circuit set forthabove in the aforementioned apparatus embodiment. In use, the convertercircuit is started up, and, in connection with the startup, theauxiliary transistor is activated for reducing a voltage stress on atleast a portion of the converter circuit in an event that the powersource is improperly coupled.

Optionally, in any of the preceding embodiments, the converter circuitmay be configured for activating the auxiliary transistor at start upfor reducing a voltage stress on at least a portion of the convertercircuit in an event that the power source is improperly coupled.

Optionally, in any of the preceding embodiments, the auxiliarytransistor may reduce the voltage stress on at least one of the pair ofserially-coupled transistors. As an additional option, the auxiliarytransistor may reduce the voltage stress on at least one of the pair ofserially-coupled diodes.

Optionally, in any of the preceding embodiments, the first capacitor maybe configured for storing a voltage amount that is less than or equal tohalf of an output voltage of the converter circuit.

Optionally, in any of the preceding embodiments, the first capacitor maybe configured for reducing a voltage stress on at least a portion of theconverter circuit

Optionally, in any of the preceding embodiments, the auxiliarytransistor may be of a same type as the pair of serially-coupledtransistors.

Optionally, in any of the preceding embodiments, the auxiliarytransistor may be of a different type as compared to the pair ofserially-coupled transistors.

Optionally, in any of the preceding embodiments, the sub-circuit mayfurther include a third capacitor coupled in parallel with the auxiliarytransistor.

Optionally, in any of the preceding embodiments, the sub-circuit mayfurther include a resistor coupled in parallel with the auxiliarytransistor.

Optionally, in any of the preceding embodiments, the auxiliarytransistor may be an insulated-gate bipolar transistor (IGBT).

Optionally, in any of the preceding embodiments, the auxiliarytransistor may be a metal oxide semiconductor field effect transistor(MOSFET).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates a converter circuit with a power source coupledcorrectly thereto, in accordance with an embodiment.

FIG. 1B illustrates the converter circuit of FIG. 1A with the powersource coupled incorrectly thereto, in accordance with an embodiment.

FIG. 1C-1 illustrates a first sub-circuit for reducing a voltage stresson at least a portion of a converter circuit in an event that a powersource is improperly coupled, in accordance with an embodiment.

FIG. 1C-2 illustrates a second sub-circuit for reducing a voltage stresson at least a portion of a converter circuit in an event that a powersource is improperly coupled, in accordance with an embodiment.

FIG. 2 illustrates a converter circuit equipped with an auxiliarytransistor for protecting at least a portion of the converter circuit atstart up, in accordance with another embodiment.

FIG. 3 illustrates a method for protecting at least a portion of aconverter circuit at start up, in accordance with an embodiment.

FIG. 4 illustrate a graph illustrating both startup and runtimeoperation of transistors of a converter circuit, in accordance with anembodiment.

FIG. 5 illustrate another graph illustrating runtime operation ofvarious inductive and capacitive components of a converter circuit, inaccordance with an embodiment.

FIG. 6 illustrates a system for reducing a voltage stress on at least aportion of a converter circuit in an event that a power source isimproperly coupled, in accordance with an embodiment.

FIG. 7 is a diagram of an exemplary processing device, in accordancewith an embodiment.

DETAILED DESCRIPTION

Various embodiments are described herein for providing a convertercircuit that incorporates an auxiliary transistor that is configured forprotecting at least a portion of the converter circuit at start-up.Specifically, in one possible embodiment, such protection may beprovided when a power source is improperly applied to the convertercircuit. This may occur, for example, when a polarity of the powersource is switched. In such case, the auxiliary transistor serves forreducing a voltage stress on at least a portion of the converter circuitwhich, in turn, reduces a chance that one or more components of theconverter circuit is damaged and the converter circuit rendered impairedor inoperable.

FIGS. 1A and 1B both illustrate a converter circuit 100 equipped with anauxiliary transistor 114 for protecting at least a portion of theconverter 100 at start up, in accordance with an embodiment.Specifically, FIG. 1A illustrates the converter circuit 100 with a powersource 111 coupled correctly thereto, in accordance with an embodiment.Further, FIG. 1B illustrates the converter circuit 100 with the powersource 111 coupled incorrectly thereto (e.g. the polarity is flipped),in accordance with an embodiment.

In one possible embodiment, the converter circuit 100 may include adirect current (DC)-DC converter for converting a source of directcurrent (DC) from one voltage level to another, and may even take theform of a multi-level boost converter. Further, while the present andother embodiments illustrate a plurality of discrete components coupledtogether, it should be noted that any one or more of the components maybe integrated with any other, as desired. Further, the term “coupled” inthe context of the present description may refer to any direct and/orindirect electrical coupling with relevant electric componentstherebetween. In other words, such electric components may be coupledwith or without intermediate components therebetween.

As shown, the converter circuit 100 includes an inductor 102 including afirst terminal 101 configured to be coupled to the power source 111, anda second terminal 103. In the context of the present description, theinductor 102 may include any inductive element that exhibits inductance.Further, the power source 111 may include any source of power. Forexample, in the context of an embodiment where the converter circuit 100takes the form of a DC-DC converter, the power source 111 may include aDC power source. In such embodiment, the power source 111 may include aphotovoltaic cell (e.g. solar panel, etc.), a DC battery, etc.

With continuing reference to FIGS. 1A-1B, the converter circuit 100further includes a pair of serially-coupled transistors (including afirst transistor 104A and a second transistor 104B) coupled to thesecond terminal 103 of the inductor 102. As shown, the pair ofserially-coupled transistors 104A, 104B have a transistor intermediatenode 105 therebetween. In various embodiments, the serially-coupledtransistors 104A, 104B (and any other transistor disclosed herein) mayinclude any type of transistor [e.g. insulated-gate bipolar transistors(IGBTs), metal oxide semiconductor field effect transistors (MOSFETs),etc.].

As shown, during use at start up (T=0), the first transistor 104A isactivated (i.e. on) and the second transistor 104B is deactivated (i.e.off). To this end, a current 130 flows as shown in FIG. 1A at start up.Subsequently, the serially-coupled transistors 104A, 104B are switchedon and off in an alternating manner. More information regarding theoperation of the converter circuit 100 and the various componentsthereof will be elaborated upon during the description of subsequentembodiments.

Further provided is a pair of serially-coupled diodes (including a firstdiode 106A and a second diode 106B) coupled to the second terminal 103of the inductor 102. The pair of serially-coupled diodes 106A, 106B havea diode intermediate node 107 therebetween. Still yet, a first capacitor108 is coupled in parallel with the serially-coupled transistors 104A,104B and the serially-coupled diodes 106A, 106B, as well as a load 121.In the context of the present description, the first capacitor 108 (andany other capacitor disclosed herein) may include any capacitive elementthat exhibits capacitance. Further, in a possible embodiment where thepower source 111 includes a photovoltaic cell (e.g. solar panel, etc.),the load 121 may include an inverter or any other subsequent componentrynecessary for processing energy collected via the photovoltaic cell.

The converter circuit 100 further includes a sub-circuit 110 having asecond capacitor 112 that is serially-coupled with an auxiliarytransistor 114. As shown, the sub-circuit 110 is coupled between thetransistor intermediate node 105 and the diode intermediate node 107. Invarious embodiments, the auxiliary transistor 114 may be of a same ordifferent type (IGBT vs. MOSFET) as compared with the pair ofserially-coupled transistors 104A, 104B.

As mentioned earlier, the auxiliary transistor 114 is configured forprotecting at least a portion of the converter circuit 100 at start-upwhen the power source 111 is improperly applied to the converter circuit100 by a polarity of the power source 111 being switched (i.e. flipped).This may occur, for example, by a photovoltaic panel (not shown) beingincorrectly attached to the converter circuit 100 during installation.

As shown in FIG. 1B, at start up, the current 132 flows in an oppositedirection when the power source 111 is improperly applied to theconverter circuit 100. In such case, the current 132 flows through thefirst transistor 104A (since it is on at startup), the auxiliarytransistor 114 (since it is on at start up), the first capacitor 112(which has no or substantially no voltage stored at start up), and thesecond diode 106B. Without the auxiliary transistor 114, the firsttransistor 104A (since it is on at startup) and the second diode 106Bwould otherwise bear the entire voltage applied by the improperlyapplied power source 111 and a likelihood of damage and/or subsequentinoperability would be increased.

However, with the auxiliary transistor 114 coupled as shown andoperating as set forth above, such auxiliary transistor 114 bears atleast a portion of the aforementioned voltage, so that the firsttransistor 104A and second diode 106B experience less voltage stress. Tothis end, the auxiliary transistor 114 serves for reducing a voltagestress on at least a portion of the converter circuit 100 (at least thefirst transistor 104A and second diode 106B). This, in turn, reduces achance that such portion of the converter circuit 100 is damaged andrendered impaired or inoperable.

More illustrative information will now be set forth regarding variousoptional architectures and uses in which the foregoing method may or maynot be implemented, per the desires of the user. It should be noted thatthe following information is set forth for illustrative purposes andshould not be construed as limiting in any manner. Any of the followingfeatures may be optionally incorporated with or without the otherfeatures described.

FIG. 1C-1 illustrates a first sub-circuit 110A for reducing a voltagestress on at least a portion of a converter circuit in an event that apower source is improperly coupled, in accordance with an embodiment. Asan option, the first sub-circuit 110A may be implemented in the contextof any one or more of the embodiments set forth in any previous and/orsubsequent figure(s) and/or the description thereof. For example, thefirst sub-circuit 110A may be implemented in the context of thesub-circuit 110 of FIG. 1A. However, it is to be appreciated that thefirst sub-circuit 110A may be implemented in other suitableenvironments.

As shown, the first sub-circuit 110A includes a capacitor 112A (e.g. thesecond capacitor 112 of FIG. 1A) serially coupled with an auxiliarytransistor 114 that reducing a voltage stress on at least a portion of aconverter circuit (e.g. the converter circuit 100 of FIG. 1A) in anevent that a power source is improperly coupled. As mentioned earlier,this is accomplished by the auxiliary transistor 114A bearing at least aportion of an improperly-applied voltage. As further shown, the firstsub-circuit 110A includes a resistor 140 coupled in parallel with theauxiliary transistor 114A. In such embodiment, such resistor 140, incombination with the auxiliary transistor 114A, may bear an increasedportion of the aforementioned improperly-applied voltage, therebyenhancing any protection afforded.

FIG. 1C-2 illustrates a second sub-circuit 110B for reducing a voltagestress on at least a portion of a converter circuit in an event that apower source is improperly coupled, in accordance with an embodiment. Asan option, the second sub-circuit 110B may be implemented in the contextof any one or more of the embodiments set forth in any previous and/orsubsequent figure(s) and/or the description thereof. For example, thesecond sub-circuit 110B may be implemented in the context of thesub-circuit 110 of FIG. 1A. However, it is to be appreciated that thesecond sub-circuit 110B may be implemented in other suitableenvironments.

As shown, the second sub-circuit 110B includes a capacitor 112B (e.g.the second capacitor 112 of FIG. 1A) serially coupled with an auxiliarytransistor 114B that reducing a voltage stress on at least a portion ofa converter circuit (e.g. the converter circuit 100 of FIG. 1A) in anevent that a power source is improperly coupled. As mentioned earlier,this is accomplished by the auxiliary transistor 114B bearing at least aportion of an improperly-applied voltage. As further shown, the secondsub-circuit 110B includes another capacitor 150 coupled in parallel withthe auxiliary transistor 114B. In such embodiment, such other capacitor150, in combination with the auxiliary transistor 114B, may bear anincreased portion of the aforementioned improperly-applied voltage,thereby enhancing any protection afforded. In yet another optionalembodiment, the other capacitor 150 may be equipped with aparallel-coupled resistor (like that shown in FIG. 1C-1), for furtherenhancing protection.

FIG. 2 illustrates a converter circuit 200 equipped with an auxiliarytransistor for protecting at least a portion of the converter circuit200 at start up, in accordance with another embodiment. As an option,the converter 200 may be implemented in the context of any one or moreof the embodiments set forth in any previous and/or subsequent figure(s)and/or the description thereof. For example, the converter circuit 200may be implemented in the context of converter circuit 100 of FIG. 1A.However, it is to be appreciated that the converter circuit 200 may beimplemented in other suitable environments.

As shown, the converter circuit 200 includes an inductor L including afirst terminal 201 configured to be coupled to a power source 211, and asecond terminal 203. The converter circuit 200 further includes a pairof serially-coupled transistors (including a first transistor Q1 and asecond transistor Q2) coupled to the second terminal 203 of the inductorL. As shown, the pair of serially-coupled transistors Q1, Q2 have atransistor intermediate node 205 therebetween.

As further shown, the serially-coupled transistors Q1, Q2 include NPNIGBT transistors, each equipped with an anti-parallel diode, in themanner shown. Specifically, the first transistor Q1 includes an emitternode coupled to ground and a common node coupled to an emitter node ofthe second transistor Q2, as shown. Still yet, the second transistor Q2includes a common node coupled to the second terminal 203 of theinductor L. In other embodiments, different types of transistors andconfigurations may be employed, as desired. For example, GaN or SiC typetransistors may be employed in another embodiment.

By this design, the serially-coupled transistors Q1, Q2 form amultiple-level (multi-level) boost converter circuit. As a result, anyvoltage stress applied by the power source 211 is shared among theserially-coupled transistors Q1, Q2. Specifically, in the multi-levelboost converter embodiment shown, any voltage stress applied by thepower source 211 is split (evenly) among the serially-coupledtransistors Q1, Q2. Further, due to the multi-level configuration, theinductor L is subjected to a greater switching frequency. In otherwords, if both transistors Q1, Q2 are switching at X Hz, the inductor L(and other passive components shown) will, due to the configuration, besubjected to 2X Hz. Thus, an amount of voltage (over time) on theinductor L is half (as compared to a single boost design) and,therefore, less current ripple will be present at an output of theinductor L and further a smaller (and thus cheaper) inductor L may beused, in some optional embodiments. It should be noted that, while theconverter circuit 200 is shown to comprise two levels, other embodimentsare contemplated where a different number of levels (e.g. three, four .. . N) are implemented.

Further provided is a pair of serially-coupled diodes (including a firstdiode D3 and a second diode D4) coupled to the second terminal 203 ofthe inductor L. The pair of serially-coupled diodes have a diodeintermediate node 207 therebetween. Specifically, the first diode D3includes an anode coupled to the second terminal 203 of the inductor L,and a cathode coupled to an anode of the second diode D4. Still yet, acathode of the second diode D4 is coupled to an output of the convertercircuit 200.

Still yet, a first capacitor Co is coupled in parallel with theserially-coupled transistors Q1, Q2 and the serially-coupled diodes D3,D4. In one embodiment, the first capacitor Co may serve as a flyingcapacitor. In use, the first capacitor Co may thus clamp an outputvoltage Vo, thereby further limiting an amount of voltage stress that iscapable of being applied to the serially-coupled transistors Q1, Q2 andthe serially-coupled diodes D3, D4. In one possible embodiment, thesize, shape, or other aspect of the first capacitor Co may be configuredto clamp a voltage amount of the first capacitor Co to be less than orequal to half of the output voltage Vo (i.e. 0.5* Vo). In variousembodiments, this may reduce voltage stress on one or more of theserially-coupled transistors Q1, Q2 and/or serially-coupled diodes D3,D4, as well as permit use of a smaller (and thus cheaper) inductor L. Asa further option, such first capacitor Co may also serve to reduce loopinductance (and lower switching loss) which may be beneficial in highervoltage/power/switching-rate applications.

The converter circuit 200 further includes a sub-circuit 210 having asecond capacitor Cdc that is serially-coupled with an auxiliarytransistor Qaux. As shown, the sub-circuit 210 is coupled between thetransistor intermediate node 205 and the diode intermediate node 207. Asfurther shown, the auxiliary transistor Qaux includes a NPN IGBTtransistor, equipped with an anti-parallel diode, in the manner shown.In other embodiments, a different type of transistor may be employed, asdesired. For example, an ion IGBT transistor or even a MOSFET may beemployed in another embodiment.

Still yet, the converter circuit 200 includes a controller 220 coupledto the gates of each of the serially-coupled transistors Q1, Q2 and theauxiliary transistor Qaux for selectively activating the same both atstart up and runtime. During runtime, the auxiliary transistor Qauxremains activated, and the converter circuit 200 alternates between afirst state with the first transistor Q1 being activated and the secondtransistor Q2 being deactivated, and a second state with the firsttransistor Q1 being deactivated and the second transistor Q2 beingactivated, with a transitory third state where both of the firsttransistor Q1 and the second transistor Q2 being deactivated.

In the first state, current flows from the power source 211 and throughthe first diode D3, the second capacitor Cdc, the auxiliary transistorQaux, and the first transistor Q1. Further, in the second state, thecurrent flows from the power source 211 and through the secondtransistor Q2, the auxiliary transistor Qaux, the second capacitor Cdc,and the second diode D4. During the transitory third state, the currentflows from the power source 211 and through the first diode D3 and thesecond diode D4. More information regarding such runtime operation willbe set forth during reference to FIGS. 4-5.

Further, at start up, the controller 220 activates the first transistorQ1 and the auxiliary transistor Qaux while deactivating the secondtransistor Q2, for a predetermined amount of time. By simultaneouslyactivating the first transistor Q1 and the auxiliary transistor Qaux atstart up, the auxiliary transistor Qaux is capable of not only chargingthe first capacitor Cdc, but also protecting the various circuitcomponents in the event of a misapplication of the voltage source 211.This may be accomplished by offloading at least a portion of a voltagestress that may be existent in the event that the power source 211 ismisapplied by the polarity thereof being flipped. This is accomplishedby permitting current to flow through the auxiliary transistor Qaux ofthe sub-circuit 210 at start up.

By this design, the converter circuit 200 is configured for activatingthe auxiliary transistor Qaux at start up for reducing a voltage stresson the first transistor Q1 and the second diode D4. More informationregarding the start up and runtime operation of the converter circuit200 will be set forth during the description of subsequent embodiments.

FIG. 3 illustrates a method 300 for protecting at least a portion of aconverter circuit at start up, in accordance with an embodiment. As anoption, the method 300 may be implemented in the context of any one ormore of the embodiments set forth in any previous and/or subsequentfigure(s) and/or the description thereof. For example, the method 300may be carried out in the context of the converter circuit 100 and/orthe converter circuit 200 of FIGS. 1A and 2, respectively. However, itis to be appreciated that the method 300 may be implemented in othersuitable environments.

As shown, the method 300 begins at start up per decision 302. In thecontext of the present description, start up may refer to aninstantaneous time or time period after power is applied to a convertercircuit (e.g. the converter circuit 100 and/or the converter circuit 200of FIGS. 1A and 2, respectively) and/or after power is applied andfurther after a controller (e.g. the controller of 220 of FIG. 2) of theconverter circuit switches the switching transistors (e.g. theserially-coupled transistors Q1, Q2 of FIG. 2) to their initial startupstates.

Once start up is initiated per decision 302, an auxiliary transistor(e.g. the auxiliary transistor Qaux of FIG. 2) is activated in operation304 by turning the same on. In connection with operation 304, acapacitor (e.g. the capacitor Cdc of FIG. 2) is charged in operation306, in preparation for runtime operation. While the operation 306 isshown to follow operation 304, it should be noted that, in otherembodiments, such operations may be simultaneously initiated inparallel.

With continuing reference to FIG. 3, it is determined in decision 308whether the charging of the capacitor (see operation 304) is complete.This may be determined, in various embodiments, by sensing a voltageacross the capacitor, or simply assuming it is charged after apredetermined amount of charging time has elapsed. If it is not charged,operations 304-306 are repeated, as shown. On the other hand, if it isdetermined in decision 308 that the charging of the capacitor iscomplete, runtime operation ensues in operation 312 whereby theserially-coupled transistors are switched on and off 180 degreesout-of-phase during use for charging and discharging an inductor (e.g.the inductor L of FIG. 2) during use. This runtime operation continuesuntil completed per decision 314.

FIGS. 4 and 5 illustrates graphs 400 and 500 illustrating runtimeoperation of a converter circuit, in accordance with an embodiment. Asan option, such runtime operation may be implemented in the context ofany one or more of the embodiments set forth in any previous and/orsubsequent figure(s) and/or the description thereof. For example, theruntime operation may be carried out in the context of the convertercircuit 100 and/or the converter circuit 200 of FIGS. 1A and 2,respectively, and/or the operation 312 of FIG. 3. However, it is to beappreciated that such runtime operation may be implemented in othersuitable environments.

As shown in the graph 400 of FIG. 4, control signals are fed, by acontroller (e.g. the controller 220 of FIG. 2), to gates/bases of afirst transistor Q1 (e.g. the first transistor Q1 of FIG. 2), a secondtransistor Q2 (e.g. the second transistor Q2 of FIG. 2), and anauxiliary transistor (e.g. the auxiliary transistor Qaux of FIG. 2) forcontrolling the switching thereof. Specifically, at a startup phase 402,the auxiliary transistor Qaux and the first transistor Q1 are activated,while the second transistor Q2 remains deactivated. During such time, acapacitor (e.g. the first capacitor Cdc) may be charged in preparationfor runtime operation.

Further, at a runtime phase 404, the auxiliary transistor Qaux remainsactivated and the first transistor Q1 and the second transistor Q2 areactivated in an alternating manner, as described above. Specifically,the first transistor Q1 is switched in accordance with a firstalternating control signal. Further, the second transistor Q2 isswitched in accordance with a second alternating control signal. Asshown, the first alternating control signal and the second alternatingcontrol signal are 180 degrees out of phase.

By including the auxiliary transistor Qaux, any misapplication ofvoltage at the beginning of the startup phase 402 (before the capacitoris charged) results in the auxiliary transistor Qaux sharing any voltagestress with other active components, thereby avoiding damage.

As shown in the graph 500 of FIG. 5, a capacitor current 502 is shown,during runtime operation, to flow through a capacitor (e.g. the secondcapacitor Cdc of FIG. 2) of the converter circuit in an alternatingmanner that coincides with the switching of the first and secondtransistors Q1, Q2. Further, an indicator current 504 is shown thatflows through an inductor (e.g. the inductor L of FIG. 2). At a 0.5 dutycycle, minimal ripple is exhibited in the indicator current 504 whichmay be desirable in some embodiments.

FIG. 6 illustrates a system 600 for reducing a voltage stress on atleast a portion of a converter circuit in an event that a power sourceis improperly coupled, in accordance with an embodiment. As an option,the system 600 may be implemented with one or more features of any oneor more of the embodiments set forth in any previous and/or subsequentfigure(s) and/or the description thereof. However, it is to beappreciated that the system 600 may be implemented in other suitableenvironments.

As shown, an inductor means in the form of an inductor module 602 isprovided for storing electrical energy in a magnetic field when electriccurrent is applied. In various embodiments, the inductor module 602 mayinclude, but is not limited to the inductors 102 and L of FIGS. 1A-2and/or any other circuitry capable of the aforementioned functionality.

Also included is a transistor means in the form of a transistor module604 in communication with the inductor module 602 for switching on andoff during runtime operation. In various embodiments, the transistormodule 604 may include, but is not limited to the transistors 104A,104B, Q1, Q2 of FIGS. 1A-2 and/or any other circuitry capable of theaforementioned functionality.

Further included is a diode means in the form of a diode module 606 incommunication with the inductor module 602 for allowing current to passin only a single direction. In various embodiments, the diode module 606may include, but is not limited to the diodes 106A, 106B, D3, D4 ofFIGS. 1A-2 and/or any other circuitry capable of the aforementionedfunctionality.

With continuing reference to FIG. 6, protection means in the form of aprotection module 608 is in communication with the diode module 606 andthe transistor module 604 for offloading at least a portion of anyvoltage stress from the diode module 606 and the transistor module 604,in response to input voltage being misapplied (e.g. due to a polaritymismatch). In various embodiments, the protection module 608 mayinclude, but is not limited to the auxiliary transistors 114, Qaux ofFIGS. 1A-2, and/or any other circuitry capable of the aforementionedfunctionality.

One or more of the foregoing embodiments may thus incorporate anauxiliary transistor that is configured for protecting at least aportion of the converter circuit at start-up. Specifically, in onepossible embodiment, such protection may be provided when a power sourceis improperly applied to the converter circuit. This may occur, forexample, when a polarity of the power source is switched. In such case,the auxiliary transistor serves for reducing a voltage stress on atleast a portion of the converter circuit which, in turn, reduces achance that one or more components of the converter circuit is damagedand the converter circuit rendered impaired or inoperable. This may, inturn, result in protection that would otherwise be foregone in systemsthat lack such componentry and/or functionality. It should be noted thatthe aforementioned potential advantages are set forth for illustrativepurposes only and should not be construed as limiting in any manner.

FIG. 7 is a diagram of an exemplary processing device 700, in accordancewith an embodiment. As an option, the processing device 700 may beimplemented in the context of the controller 220 of FIG. 2. However, itis to be appreciated that the processing device 700 may be implementedin any desired environment.

As shown, the processing device 700 includes at least one processor 702which is connected to a bus 712. The processing device 700 also includesmemory 704 [e.g., hard disk drive, solid state drive, random accessmemory (RAM), etc.] coupled to the bus 712. The memory 704 may includeone or more memory components, and may even include different types ofmemory. Further included is a communication interface 708 (e.g.local/remote network interface, memory access interface, etc.) and aninput/output (I/O) interface 710 (e.g. display, speaker, microphone,touchscreen, touchpad, mouse interface, etc.).

The processing device 700 may also include a secondary storage 706. Thesecondary storage 706 coupled to the bus 712 and/or to other componentsof the processing device 700. The secondary storage 706 can include, forexample, a hard disk drive and/or a removable storage drive,representing a floppy disk drive, a magnetic tape drive, a compact diskdrive, etc. The removable storage drive reads from and/or writes to aremovable storage unit in a well-known manner.

Computer programs, or computer control logic algorithms, may be storedin the memory 704, the secondary storage 706, and/or any other memory,for that matter. Such computer programs, when executed, enable theprocessing device 700 to perform various functions (as set forth above,for example). Memory 704, secondary storage 706 and/or any other storagecomprise non-transitory computer-readable media.

In one embodiment, the at least one processor 702 executes instructionsin the memory 704 or in the secondary storage 706 to control a converter(e.g. the converter 100 or 200 of FIGS. 1 and 2, respectively). It isnoted that the techniques described herein, in an aspect, are embodiedin executable instructions stored in a computer readable medium for useby or in connection with an instruction execution machine, apparatus, ordevice, such as a computer-based or processor-containing machine,apparatus, or device. It will be appreciated by those skilled in the artthat for some embodiments, other types of computer readable media areincluded which may store data that is accessible by a computer, such asmagnetic cassettes, flash memory cards, digital video disks, Bernoullicartridges, random access memory (RAM), read-only memory (ROM), or thelike.

As used here, a “computer-readable medium” includes one or more of anysuitable media for storing the executable instructions of a computerprogram such that the instruction execution machine, system, apparatus,or device may read (or fetch) the instructions from the computerreadable medium and execute the instructions for carrying out thedescribed methods. Suitable storage formats include one or more of anelectronic, magnetic, optical, and electromagnetic format. Anon-exhaustive list of conventional exemplary computer readable mediumincludes: a portable computer diskette; a RAM; a ROM; an erasableprogrammable read only memory (EPROM or flash memory); optical storagedevices, including a portable compact disc (CD), a portable digitalvideo disc (DVD), a high definition DVD (HD-DVD™), a BLU-RAY disc; orthe like.

Computer-readable non-transitory media includes all types of computerreadable media, including magnetic storage media, optical storage media,and solid state storage media and specifically excludes signals. Itshould be understood that the software can be installed in and sold withthe devices described herein. Alternatively the software can be obtainedand loaded into the devices, including obtaining the software via a discmedium or from any manner of network or distribution system, including,for example, from a server owned by the software creator or from aserver not owned but used by the software creator. The software can bestored on a server for distribution over the Internet, for example.

It should be understood that the arrangement of components illustratedin the Figures described are exemplary and that other arrangements arepossible. It should also be understood that the various systemcomponents defined by the claims, described below, and illustrated inthe various block diagrams represent logical components in some systemsconfigured according to the subject matter disclosed herein.

For example, one or more of these system components may be realized, inwhole or in part, by at least some of the components illustrated in thearrangements illustrated in the described Figures. In addition, while atleast one of these components are implemented at least partially as anelectronic hardware component, and therefore constitutes a machine, theother components may be implemented in software that when included in anexecution environment constitutes a machine, hardware, or a combinationof software and hardware.

More particularly, at least one component defined by the claims isimplemented at least partially as an electronic hardware component, suchas an instruction execution machine (e.g., a processor-based orprocessor-containing machine) and/or as specialized circuits orcircuitry (e.g., discrete logic gates interconnected to perform aspecialized function). Other components may be implemented in software,hardware, or a combination of software and hardware. Moreover, some orall of these other components may be combined, some may be omittedaltogether, and additional components may be added while still achievingthe functionality described herein. Thus, the subject matter describedherein may be embodied in many different variations, and all suchvariations are contemplated to be within the scope of what is claimed.

In the description above, the subject matter is described with referenceto acts and symbolic representations of operations that are performed byone or more devices, unless indicated otherwise. As such, it will beunderstood that such acts and operations, which are at times referred toas being computer-executed, include the manipulation by the processor ofdata in a structured form. This manipulation transforms the data ormaintains it at locations in the memory system of the computer, whichreconfigures or otherwise alters the operation of the device in a mannerwell understood by those skilled in the art. The data is maintained atphysical locations of the memory as data structures that have particularproperties defined by the format of the data. However, while the subjectmatter is being described in the foregoing context, it is not meant tobe limiting as those of skill in the art will appreciate that various ofthe acts and operations described hereinafter may also be implemented inhardware.

To facilitate an understanding of the subject matter described herein,many aspects are described in terms of sequences of actions. At leastone of these aspects defined by the claims is performed by an electronichardware component. For example, it will be recognized that the variousactions may be performed by specialized circuits or circuitry, byprogram instructions being executed by one or more processors, or by acombination of both. The description herein of any sequence of actionsis not intended to imply that the specific order described forperforming that sequence must be followed. All methods described hereinmay be performed in any suitable order unless otherwise indicated hereinor otherwise clearly contradicted by context.

The use of the terms “a” and “an” and “the” and similar referents in thecontext of describing the subject matter (particularly in the context ofthe following claims) are to be construed to cover both the singular andthe plural, unless otherwise indicated herein or clearly contradicted bycontext. Recitation of ranges of values herein are merely intended toserve as a shorthand method of referring individually to each separatevalue falling within the range, unless otherwise indicated herein, andeach separate value is incorporated into the specification as if it wereindividually recited herein. Furthermore, the foregoing description isfor the purpose of illustration only, and not for the purpose oflimitation, as the scope of protection sought is defined by the claimsas set forth hereinafter together with any equivalents thereof entitledto. The use of any and all examples, or exemplary language (e.g., “suchas”) provided herein, is intended merely to better illustrate thesubject matter and does not pose a limitation on the scope of thesubject matter unless otherwise claimed. The use of the term “based on”and other like phrases indicating a condition for bringing about aresult, both in the claims and in the written description, is notintended to foreclose any other conditions that bring about that result.No language in the specification should be construed as indicating anynon-claimed element as essential to the practice of the embodiments asclaimed.

The embodiments described herein include the one or more modes known tothe inventor for carrying out the claimed subject matter. It is to beappreciated that variations of those embodiments will become apparent tothose of ordinary skill in the art upon reading the foregoingdescription. The inventor expects skilled artisans to employ suchvariations as appropriate, and the inventor intends for the claimedsubject matter to be practiced otherwise than as specifically describedherein. Accordingly, this claimed subject matter includes allmodifications and equivalents of the subject matter recited in theclaims appended hereto as permitted by applicable law. Moreover, anycombination of the above-described elements in all possible variationsthereof is encompassed unless otherwise indicated herein or otherwiseclearly contradicted by context.

What is claimed is:
 1. An apparatus, comprising: a converter circuitincluding: an inductor including a first terminal configured to becoupled to a power source, and a second terminal; a pair ofserially-coupled transistors coupled to the second terminal of theinductor, the pair of serially-coupled transistors having a transistorintermediate node therebetween; a pair of serially-coupled diodescoupled to the second terminal of the inductor, the pair ofserially-coupled diodes having a diode intermediate node therebetween; afirst capacitor coupled in parallel with the serially-coupledtransistors and the serially-coupled diodes; and a sub-circuit includinga second capacitor serially-coupled with an auxiliary transistor, thesub-circuit coupled between the transistor intermediate node and thediode intermediate node; wherein the converter circuit is configured foractivating the auxiliary transistor at start up for reducing a voltagestress on at least a portion of the converter circuit in an event thatthe power source is improperly coupled.
 2. The apparatus of claim 1,wherein the auxiliary transistor reduces the voltage stress on at leastone of the pair of serially-coupled transistors.
 3. The apparatus ofclaim 1, wherein the auxiliary transistor reduces the voltage stress onat least one of the pair of serially-coupled diodes.
 4. The apparatus ofclaim 1, wherein the first capacitor is configured for storing a voltageamount that is less than or equal to half of an output voltage of theconverter circuit.
 5. The apparatus of claim 1, wherein the firstcapacitor is configured for reducing a voltage stress on at least aportion of the converter circuit.
 6. The apparatus of claim 1, whereinthe auxiliary transistor is of a same type as the pair ofserially-coupled transistors.
 7. The apparatus of claim 1, wherein theauxiliary transistor is of a different type as compared to the pair ofserially-coupled transistors.
 8. The apparatus of claim 1, wherein thesub-circuit further includes a third capacitor coupled in parallel withthe auxiliary transistor.
 9. The apparatus of claim 1, wherein thesub-circuit further includes a resistor coupled in parallel with theauxiliary transistor.
 10. The apparatus of claim 1, wherein theauxiliary transistor is an insulated-gate bipolar transistor (IGBT). 11.The apparatus of claim 1, wherein the auxiliary transistor is a metaloxide semiconductor field effect transistor (MOSFET).
 12. A method,comprising: starting up a converter circuit, the converter circuitincluding: an inductor including a first terminal configured to becoupled to a power source, and a second terminal; a pair ofserially-coupled transistors coupled to the second terminal of theinductor, the pair of serially-coupled transistors having a transistorintermediate node therebetween; a pair of serially-coupled diodescoupled to the second terminal of the inductor, the pair ofserially-coupled diodes having a diode intermediate node therebetween; afirst capacitor coupled in parallel with the serially-coupledtransistors and the serially-coupled diodes; and a sub-circuit includinga second capacitor serially-coupled with an auxiliary transistor, thesub-circuit coupled between the transistor intermediate node and thediode intermediate node; and in connection with the startup, activatingthe auxiliary transistor for reducing a voltage stress on at least aportion of the converter circuit, wherein the auxiliary transistorreduces the voltage stress on the at least portion of the convertercircuit in an event that the power source is improperly coupled.
 13. Themethod of claim 12, wherein the auxiliary transistor reduces the voltagestress on at least one of the pair of serially-coupled transistors. 14.The method of claim 12, wherein the auxiliary transistor reduces thevoltage stress on at least one of the pair of serially-coupled diodes.15. The method of claim 12, and further comprising: storing, utilizingthe first capacitor, a voltage amount that is less than or equal to halfof an output voltage of the converter circuit.
 16. The method of claim12, and further comprising: reducing, utilizing the first capacitor, thevoltage stress on at least a part of the converter circuit.
 17. Themethod of claim 12, wherein the auxiliary transistor is of a same typeas the pair of serially-coupled transistors.
 18. The method of claim 12,wherein the auxiliary transistor is of a different type as compared tothe pair of serially-coupled transistors.
 19. The method of claim 12,wherein the sub-circuit further includes a third capacitor coupled inparallel with the auxiliary transistor.
 20. The method of claim 12,wherein the sub-circuit further includes a resistor coupled in parallelwith the auxiliary transistor.